AI & Compute
Why Chips Are Packaged, Not Just Printed
Assembling processors, memory and interposers into a single package has become as difficult as printing the transistors, and it now limits how many accelerators can be produced.
Public attention on semiconductor manufacturing focuses on lithography and feature size. The stage that follows, in which finished silicon is assembled into a working package, has become an equally hard constraint.
A modern accelerator is several pieces of silicon
Rather than one large die, high-end parts combine multiple compute dies with stacks of memory, mounted together on a substrate that carries connections between them.
This is done because very large dies suffer yield problems: a single defect ruins the whole thing, and the probability rises with area.
Splitting the design into smaller pieces improves yield and allows different parts to be manufactured on the process best suited to them.
The connections between dies are the difficult part
Signals must pass between dies at enormous rates with tight timing, which requires connection densities far beyond conventional circuit boards.
Silicon interposers and fine-pitch bonding provide that density, and both require specialized equipment and processes that few facilities operate.
Because these steps come after wafer fabrication, they can bottleneck output even when the front-end fabs have capacity available.
Stacked memory has to be attached without warping
Memory arrives as a stack of thin dies bonded together, and attaching that stack alongside a hot processor introduces mechanical stress as materials expand at different rates.
Warpage during assembly is a major source of yield loss, and a defect at this stage destroys expensive components that were individually good.
The cost of a failure late in the process is a large part of why advanced packaging capacity is expensive to expand.
Heat removal is designed into the package
Concentrating enormous power in a small area makes the path from silicon to cooling system a first-order design concern rather than an afterthought.
Lids, thermal interface materials and, increasingly, structures that bring liquid close to the die are decided together with the electrical layout.
This is why the transition to liquid cooling in data centers is driven by package-level physics rather than by facility preference.
Why capacity here shapes availability
Advanced packaging is provided by a small number of facilities, and building more takes years of equipment lead time and process qualification.
When demand for accelerators rises quickly, this stage often becomes the limiting step, which is why supply constraints persist even when wafer capacity appears adequate.
Buyers negotiating for future hardware are therefore often really negotiating for packaging and memory allocation, since those are the components that cannot be conjured quickly at any price.
